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CXD1807Q
CD-G Decoder For the availability of this product, please contact the sales office.
Description The CXD1807Q has functions to decode CD-G commands written in the CD subcode and write them into the DRAM to display them. It also has a built-in RGB 4-bit D/A converter. By adding 256K bits of DRAM and a video encoder, a CD graphics system can be configured. Functions * Real-time correction of subcode errors * Powerful protection circuit for subcode synchronization * RAM for color look-up table * Compatible with both NTSC and PAL * 4-bit DAC for RGB * 80-pin QFP Applications CD-G decoder Structure Silicon gate CMOS IC Absolute Maximum Ratings (Ta = 25C) * Supply voltage VDD VSS-0.5 to +7.0 * Input voltage VI VSS-0.5 to VDD +0.5 * Output voltage VO VSS-0.5 to VDD +0.5 * Operating temperature Topr -20 to +75 * Storage temperature Tstg -55 to +150 Recommended Operating Conditions * Supply voltage DVDD 50.5 AVDD 50.5 * Ambient temperature Ta -20 to +75 80 pin QFP (Plastic)
V V V C C
V V C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E94643-ST
CXD1807Q
Block Diagram
68, 72, 76 AVDD Buffer RAM SCOR 35 WFCK 36 EXCK 37 SBSO 38 MUTE 34
SUB CODE Interface
70, 74, 78 AVSS
Buffer RAM Manager
CD-G Instruction Decode
39 CDG
Error Correction
CLK 26 DIN 27 XLT 28
CPU Interface
VRAM Graphics Control
46 OE1 47 WE1 48 RAS1
XRST 24 XIN 18 XOUT 17 XTL1 20 XTL2 19 CK Gen. Display Address Generation
DRAM R/W Control
49 CAS1 55 to A10 to A17 62 50 51 53 54 D10 to D13
INTR 15 NTSC 16
CLUT RAM Control
CLUT RAM 21 CBAR 22 APCJ RGB Output Control 25 VOFF
FSC1 80 CBLK 1
SYNC Gen.
75 VB 66 IRF 67 VRF 71 VG D/A R0 to R3 G0 to G3 B0 to B3 69 ROUT 73 GOUT 77 BOUT
VSYC 3 HSYC 4 CSYC 5
8, 33 DVDD
2, 7, 12, 23, 32, 42, 52, 63 DVSS
6, 9 to 11, 13, 14, 29 to 31, 40, 41, 43 to 45 TST0 to TSTD
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CXD1807Q
Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Symbol CBLK DVSS VSYC HSYC CSYC TST8 DVSS DVDD TST9 TST4 TST5 DVSS TST6 TST7 INTR NTSC XOUT XIN XTL2 XTL1 CBAR APCJ DVSS XRST VOFF CLK DIN XLT TSTA TSTB TSTC DVSS DVDD MUTE I/O O -- O O O O -- -- O I I -- I I I I O I O I I I -- I I I I I O O O -- -- I Description Composite blanking signal; negative logic Digital ground Vertical sync signal; negative logic Horizontal sync signal; negative logic Composite sync signal; negative logic Test pin Digital ground Digital power supply Test pin Test pin Test pin Digital ground Test pin Test pin Interlace/non-interlace (High/Low) switching signal NTSC/PAL (High/Low) select signal 14.31818MHz (NTSC 4fsc) crystal oscillator circuit output 14.31818MHz (NTSC 4fsc) crystal oscillator circuit input 17.734475MHz (PAL 4fsc) crystal oscillator circuit output 17.734475MHz (PAL 4fsc) crystal oscillator circuit input Color bar output select signal; positive logic APC-adjusting input signal; positive logic Digital ground Reset input signal; negative logic R, G, B output mute select signal; positive logic Data write clock signal from CPU Serial data input signal from CPU Data latch signal from CPU Test pin Test pin Test pin Digital ground Digital power supply Subcode data mute signal; positive logic
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CXD1807Q
Pin No. 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71
Symbol SCOR WFCK EXCK SBSO CDG TSTD TST3 DVSS TST2 TST1 TST0 OE1 WE1 RAS1 CAS1 D10 D11 DVSS D12 D13 A10 A11 A12 A13 A14 A15 A16 A17 DVSS N.C. N.C. IRF VRF AVDD1 ROUT AVSS1 VG
I/O I I O I O O I -- I I I O O O O I/O I/O -- I/O I/O O O O O O O O O -- -- -- O I -- O -- I
Description Subcode sync signal from CD DSP; positive logic Write frame clock signal from CD DSP Subcode data readout clock signal to CD DSP Subcode data P to W serial input signal from CD DSP Disc identification signal Test pin Test pin Digital ground Test pin Test pin Test pin DRAM output enable signal; negative logic DRAM write enable signal; negative logic DRAM row address strobe signal; negative logic DRAM column address strobe signal; negative logic DRAM data bus (LSB) DRAM data bus Digital ground DRAM data bus DRAM data bus (MSB) DRAM address (LSB) DRAM address DRAM address DRAM address DRAM address DRAM address DRAM address DRAM address (MSB) Digital ground
Connect a resistance 15 times the output resistance. Sets the full-scale value of RGB output signal. Analog power supply for R channel/DA converter Analog red signal output Analog ground for R channel/DA converter Connect a power supply through an approximately 0.1F capacitor. -4-
CXD1807Q
Pin No. 72 73 74 75 76 77 78 79 80
Sumbol AVDD2 GOUT AVSS2 VB AVDD3 BOUT AVSS3 N.C. FSC1
I/O -- O -- O -- O -- -- O
Description Analog power supply for G channel/DA converter Analog green signal output Analog ground for G channel/DA converter Connect GND through an approximately 0.1F capacitor. Analog power supply for B channel/DA converter Analog blue signal output Analog ground for B channel/DA converter
3.58MHz (NTSC), 4.43MHz (PAL) clock output (sub carrier clock signal)
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CXD1807Q
Electrical Characteristics 1. DC Characteristics Item Supply current High level input voltage (1) Low level input voltage (1) High level input voltage (2) Low level input voltage (2) High level input voltage (3) Low level input voltage (3) TTL Schmitt hysteresis High level input voltage (4) Low level input voltage (4) CMOS Schmitt hysteresis Input current of pull-up input (5) High level output voltage (6) Low level output voltage (6) High level output voltage (7) Low level output voltage (7) High level output voltage (8) Low level output voltage (8) Input leak current Oscillation cell logic threshold Oscillation cell high level input voltage Oscillation cell low level input voltage Oscillation cell feedback resistance Oscillation cell high level output voltage Oscillation cell low level output voltage Symbol IDD VIH1 VIL1 VIH2 VIL2 Vt1 + Vt1 - Vt1 + - Vt1 - Vt2 + Vt2 - Vt2 + - Vt2 - IIN VOH1 VOL1 VOH2 VOL2 VOH3 VOL3 IIL1 LVth VIH VIL RFB VOH VOL VIN = VSS or VDD IOH = -3mA IOL = 3mA 250k 0.5VDD 0.5VDD 1M 0.7VDD 0.3VDD 2.5M VIN = 0V IOH1 = -2mA IOL1 = 4mA IOH1 = -4mA IOL1 = 8mA IOH1 = -6mA IOL1 = 4mA -10 0.5VDD VDD-0.8 0.4 10 VDD-0.8 0.4 -40 VDD-0.8 0.4 0.6 -100 -240 0.8VDD 0.2VDD 0.4 2.2 0.8 0.7VDD 0.3VDD (VDD = 5V10%, VSS = 0V, Topr = -20 to +75C) Conditions Operating state 2.2 0.8 Min. Typ. Max. 100 Unit mA V V V V V V V V V V A V V V V V V A V V V V V
1-1. Classification of input pins (1) TTL level input: DIN, XLT, D10 to D13 (2) CMOS level input: INTR, NTSC, SCOR, SBSO, MUTE, APCJ, VOFF, CBAR, TST0 to TST7 (3) TTL Schmitt input: CLK (4) CMOS Schmitt input: XRST, WFCK (5) Pull-up input: D10 to D13 -6-
CXD1807Q
1-2. Classification of output pins (6) Normal output: FSC1, CBLK, VSYC, HSYC, CSYC, A10 to A17, D10 to D13, OE1, WE1, EXCK, TST8 to TSTD (7) Powered output: CDG (8) Proportional output: RAS1, CAS1 1-3. Oscillation cell Input : XIN, XTL1 Output : XOUT, XTL2 1-4. I/O pin capacitances Item Input pin Output pin Input/output pin Symbol CIN COUT CI/O Min. (VDD = VI = 0V, f = 1MHz) Typ. Max. 9 11 11 Unit pF pF pF
2. AC Characteristics (VDD = 5V10%, VSS = 0V, Topr = -20 to +75C, Output Load = 75pF) 2-1. CPU interface (1) Write
Twck 1/Fck Twck
CLK
DIN Tsu XLT Th
Tcld
Twl
Item Clock frequency Clock pulse width Setup time (for CLK ) Hold time (for CLK ) CLK - XLT delay time Latch pulse width
Symbol Fck Twck Tsu Th Tcld Twl
Min.
Typ.
Max. 0.65
Unit MHz ns ns ns ns ns
750 300 300 300 750
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CXD1807Q
2-2. DRAM interface
(1) Read (page mode)
Tras RAS1 Trcd CAS1 Tasr A10 to A17 row Trah D10 to D13 Tddc WE1 Tdhc high col Tasc col Tcah col row Tcas Tpc Trp
OE1
low
(2) Write (page mode)
Tras RAS1 Trcd CAS1 Tasr A10 to A17 row Trah D10 to D13 Tds Tdh WE1 col Tasc col Tcah col row Tcas Tpc Trp
OE1 Todd
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CXD1807Q
(Tw = 1/f, f: master clock frequency) Item RAS pulse width RAS precharge width RAS - CAS delay time CAS pulse width Page mode cycle time Row address setup time (for RAS, ) Row address hold time (for RAS, ) Column address setup time (for CAS, ) Column address hold time (for CAS, ) Data input delay time (for CAS, ) Data float time (relative to CAS, ) Data output setup time (for CAS, ) Data output hold time (for CAS, ) Data output delay time (for OE, ) Symbol Tras Trp Trcd Tcas Tpc Tasr Trah Tasc Tcah Tddc Tdhc Tds Tdh Todd 10 Tw -50 Tw -15 Tw 2Tw -45 Tw -15 Tw -35 Tw Tw -10 Min. 3Tw -10 2Tw 2Tw Tw 2Tw Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
(3) Read modify write
Trwc Tras RAS1 Trcd CAS1 Trah A10 to A17 row Tasr D10 to D13 Tasc in Tdsi WE1 Tcwd OE1 Tcod Toeh Tds out Twp Tcah column Tdhi Tdh row Tcas
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CXD1807Q
(Tw = 1/f, f: master clock frequency) Item RAS pulse width Read/write cycle RAS-CAS delay time CAS pulse width CAS-WE delay time WE pulse width OE hold time (for WE ) CAS-OE delay time Row address setup time (for RAS ) Row address hold time (for RAS ) Column address setup time (for CAS ) Column address hold time (for CAS ) Data input setup time (for OE ) Data input hold time (for OE ) Data output setup time (for WE ) Data output hold time (for WE ) Symbol Tras Trwc Trcd Tcas Tcwd Twp Toeh Tcod Tasr Trah Tasc Tcah Tdsi Tdhi Tds Tdh 2Tw - 45 Tw - 15 Tw - 35 5Tw 35 0 Tw - 50 Tw - 15 Min. Typ. 7Tw 9Tw 2Tw 5Tw 4Tw Tw Tw 2Tw Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
3. Built-in DAC Characteristics Recommended operating conditions Item Supply voltage Symbol AVDD1, AVDD2, AVDD3 Ratings 4.5 to 5.5 0.5 to 2.0 Unit V V
Reference input voltage VRF
Electrical characteristics Item Resolution Differential linearity error Integral linearity error Full-scale output voltage Full-scale output current Assured precision output voltage range
(VDD = 5V, VRF = 2V, R = 200, Ta = 25C) Symbol Conditions n ED EL VFS IFS VOC 0.5 -0.5 -1.0 1.9 2.0 10 2.0 Min. Typ. 4 +0.5 +1.0 2.1 15 2.1 Max. Unit bit LSB LSB V mA V
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CXD1807Q
Description of Functions 1. Pin Description 1-1. Subcode data interface Inputs subcode data and subcode sync detection signals using the following pins. These pins can be directly connected to Sony signal processing LSI for CD. 1) SCOR Inputs the signal that indicates detection of either subcode sync S0 or S1. Connect this pin to the SCOR pin of CD DSP. 2) WFCK Inputs WFCK (Write Frame Clock). Connect this pin to the WFCK pin of CD DSP. 3) EXCK Outputs the clock to read data from the SBSO pin. Connect this pin to the EXCK pin of CD DSP. 4) SBSO Serially inputs the subcode data P to W. Connect this pin to the SBSO pin of CD DSP. 5) MUTE Inputs the signal to mute subcode data inputs. This pin is in the mute state when High signal is input. 1-2. CPU interface Inputs data and sends commands to the CXD1807Q using the following pins. 1) CLK Inputs the clock to input serial data from the external CPU. 2) DIN Inputs serial data from the external CPU. 3) XLT Inputs the signal to latch serial data from the external CPU. The pin latches serial data at the falling edge of this signal. 1-3. DRAM interface The screen data are stored in the external DRAM. The DRAM read/write function is controlled using the following pins. Use a 64K x 4-bit DRAM with an access time of 100ns or less. 1) RAS1 Indicates the row address is effective. Connect this pin to the RAS pin of the external DRAM. 2) CAS1 Indicates the column address is effective. Connect this pin to the CAS pin of the external DRAM. 3) A10 to A17 (8 pins) Outputs DRAM addresses. Connect these pins to the A0 to A7 pins of the external DRAM, respectively. 4) D10 to D13 (4 pins) Inputs and outputs DRAM data. Connect these pins to the D0 to D3 pins of the external DRAM, respectively. 5) WE1 Outputs the write enable signal of DRAM. Connect this pin to the WE pin of the external DRAM. 6) OE1 Outputs the output enable signal of DRAM. Connect this pin to the OE pin of the external DRAM. - 11 -
CXD1807Q
1-4. Sync signal generation Various sync signals are output from the following pins by dividing the clock frequency. 1) INTR Switches either interlace or non-interlace to display the image. The interlace display selected for High. 2) NTSC Inputs the signal for selecting either NTSC or PAL mode to output the sync signal. The NTSC mode selected for High. 3) FSC1 Outputs the signal with a quarter frequency of clock input to the XIN pin (NTSC) or to the XTL1 pin (PAL). This signal has the same frequency as the color signal subcarrier. 4) CBLK Outputs the composite blanking signal. Switched to Low during the blanking period. 5) VSYC Outputs the vertical sync signal. Negative logic. 6) HSYC Outputs the horizontal sync signal. Negative logic. 7) CSYC Outputs the composite sync signal. Negative logic. 1-5. RGB data output 1) VOFF Mute input for R, G, and B outputs. When this pin is set to High, all the screens for the RGB output show the color set by the external CPU; the initial color setting is blue. 2) CBAR When this pin is set to High, a color bar pattern is output from the RGB pin; the bar width varies with the color. 3) APCJ When this pin is set to High, a black-and-white cross-hatch screen is output from the RGB pin. 4) ROUT The red data analog output. It can be extracted by connecting a resistor; an output resistance of 200 should be connected. 5) GOUT The green data analog output. It can be extracted by connecting a resistor; an output resistance of 200 should be connected. 6) BOUT The blue data analog output. It can be extracted by connecting a resistor; an output resistance of 200 should be connected. 7) VB Connect this pin to ground through a capacitor of approximately 0.1F. 8) IRF Connect a resistor equal to 15 times the RGB signal output resistance (3k resistance). 9) VRF Sets the full-scale output value through external resistance dividing. 10) VG Connect this pin to a power supply through a capacitor of approximately 0.1F. - 12 -
CXD1807Q
1-6. Clock 1) XIN, XOUT In the NTSC mode, input the master clock (14.31818MHz) of this LSI. An oscillation circuit can be made by connecting X'TAL to the XIN and XOUT pins. (The capacitor values depend on the crystal oscillator.) When not used, XIN should be connected to GND. 2) XTL1, XTL2 In the PAL mode, input the master clock (17.734475MHz) of this LSI. An oscillation circuit can be made by connecting the X'TAL to the XTL1 and XTL2 pins. (The capacitor values depend on the crystal oscillator.) When not used, XTL1 should be connected to GND. 1-7. Others 1) XRST Reset input. When this pin is set to Low, this LSI is reset. 2) CDG The output goes to High after detection of a subcode input CD-G command. This signal is cleared by a reset input from the XRST pin. 3) TST0 to TSTD Test pins. (These pins used for the shipping test of the LSI.) Fix the TST0 to TST7 pins to Low. 2. CPU Interface Each command can be input to this LSI by inputting address or data to the three pins; DIN, XLT and CLK, with the timing shown in Fig. 1. Description of Each Command The following explains the various functions of each command. The relations between the address and data of each command are summarized in Table 1. 2-1. Color setting commands for VOFF (address = CH) The VOFF pin can make the screen monochromatic; the color then used is set using this command. D7 D6 D5 D4 D3 D2 D1 -- D0 --
RGB select (MSB)
colour data
The color is set using 4 bits for each of R, G and B. RGB select is used to select which of the colors R, G or B is to be set. D7 0 0 1 1 D6 0 1 0 1 Color selected Red Green Blue Don't care
On reset, the values Red=[0000], Green=[0000], Blue=[1111] are set.
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CXD1807Q
2-2. Graphic channel setting command (address = DH) This command sets and releases each of the 16 graphic channels. D7 D6 D5 D4 D3 Channel ON D2 -- D1 -- D0 --
(MSB) Channel No.
(1) Channel ON High ... The channel selected by the channel No. is set to High. Low ... The channel selected by the channel No. is reset to Low. Of the CD-G commands, the Write FONT and EOR FONT commands are executed only when the channel No. for those commands is set. On reset, only CH0 and CH1 can be set and the others are released. Fig. 1. CPU interface data format
CLK
DIN
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
A3
XLT LSB Data MSB LSB Address
Table 1. List of CPU commands Register name 6 7 8 9 A B C D E F Command Reserved Reserved Reserved Reserved Reserved Reserved Color setting for VOFF Graphic channel setting Reserved Reserved Address A3 0 0 1 1 1 1 1 1 1 1 A2 1 1 0 0 0 0 1 1 1 1 A1 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 RGB Select Color Data Color Data (MSB 2bit) (LSB 2bit) ch-ON -- -- -- -- -- D7 Data 1 D6 D5 D4 D3 Data 2 D2 D1 D0
Channel No.
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Application Circuit (NTSC mode)
64k x 4bit DRAM
48 49 47
46 55 to 62 50, 51, 53, 54 D10 to 13 ROUT 69 GOUT 73 R G B 200W 2 3 4
62 36 WFCK 37 EXCK 38 SBSO BOUT 77
CXD2500BQ
65
64
26 CLK 27 DIN 28 XLT 34 MUTE 24 XRST FSC1 80 CSYC 5 AVDD 10 VRF 67 3kW IRF 66 6
RAS1
CAS1
WE1
OE1
A10 to 17
63 35 SCOR
XIN
XOUT
NTSC
INTR
CBAR
VB
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CXD1807Q
18 17 16 15 21 75 DVDD DVSS X' tal 14.31818MHz
VG 71
AVSS
CXA1645P/M
RESET
AVSS
17
Microcomputer
CXD1807Q
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
Fig.2. NTSC Screen Composition
HSYNC 44d 288d 45d
455dot
VSYNC 10d
68d
17H
25H (25.5) H
BLANK
BORDER DISPLAY AREA
262H (262.5H)
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288dot x 192H
192H
25H (25.5) H 3H
CXD1807Q
(
) Interlace display inside parentheses.
Fig. 3. PAL Screen Composition
HSYNC 84d 288d 88d
567dot
VSYNC 13d
94d
22.5H
48H (48.5) H
BLANK DISPLAY AREA
BORDER
312H (312.5H)
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288dot x 192H
192H
47H (47.5) H
2.5H
CXD1807Q
(
) Interlace display inside parentheses.
CXD1807Q
Package Outline
Unit: mm
80PIN QFP (PLASTIC)
23.9 0.4 + 0.4 20.0 - 0.1 64 41 + 0.1 0.15 - 0.05 0.15
65
40
+ 0.4 14.0 - 0.1
17.9 0.4
A 80 25 + 0.2 0.1 - 0.05
0.8
0.12
M
+ 0.15 0.35 - 0.1
+ 0.35 2.75 - 0.15
0 to 10 DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL EPOXY RESIN SOLDER PLATING COPPER / 42 ALLOY 1.6g QFP-80P-L01 LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT
SONY CODE EIAJ CODE JEDEC CODE
QFP080-P-1420-A
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0.8 0.2
1
24
16.3

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